A framework for performance-based program partitioning

  • Authors:
  • Ram Subramanian;Santosh Pande

  • Affiliations:
  • Univ. of Cincinnati, Cincinnati, OH;Univ. of Cincinnati, Cincinnati, OH

  • Venue:
  • Progress in computer research
  • Year:
  • 2001

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Abstract

Most of the reported work in the Parallelizing Compilers literaturefocuses on analyzing program characteristics such as thedependencies, loop structures, memory reference patterns etc. tooptimize the generated parallel code [3, 2, 7, 8, 14, 10].Unfortunately, parallelizing compilers have very little or noknowledge of the actual run time behavior of the synthesized codeon the underlying hardware due to the complex behavior of theunderlaying hardware and software subsystems. This interactioncould significantly affect the performance of the generated codeand must be considered during program partitioning phases of thecompiler. In this paper, we present an efficient and accurateperformance model based program partitioning approach for parallelarchitectures. We introduce the concept of behavioral edges forcapturing the interactions between computation and communicationthrough parametric functions. We present an efficient algorithm toidentify behavioral edges, modify costs using the behavioral edgesand adapt the schedule to improve schedule length. The programpartitioning phase uses the static estimates computed using thebehavioral edges and partitioning is iteratively performed usingthe ordering PDG based on computed intervals. A significantperformance improvement (factor of 10 in many cases) isdemonstrated by using our framework.