Integrating formal verification in an online judge for e-Learning logic circuit design
Proceedings of the 43rd ACM technical symposium on Computer Science Education
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From the Publisher:With this book, you can:Start writing synthesizable Verilog models quickly. See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic. Learn techniques to help avoid having functional mismatches. Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.About the Author:J. Bhasker is the chair of the IEEE PAR 1364.1 Verilog Synthesis Interoperability Working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the Archsyn synthesis system developed at Bell Labs. He has taught Verilog HDL and Verilog HDL synthesis to many AT&T / Lucent designers. He is also the author of the bestselling book A Verilog HDL Primer.