A new approach of stuck-at fault simulation for synchronous digital systems

  • Authors:

  • Leonard J. Tung;Mark Mills

  • Affiliations:

  • The Florida State Univ.;Naval Coastal Systems Center, Panama City, FL

  • Venue:
  • ANSS '87 Proceedings of the 20th annual symposium on Simulation
  • Year:
  • 1987

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Abstract

A new approach is proposed for stuck-at fault simulations. Stuck-at fault models in the approach are developed via the component connection model. Based on the approach, a simulation program is designed. A combinational logic circuit is simulated and the test sets are generated using the program.