The reliability of computer memories
Scientific American
The Reliability of Systems with Two Levels of Fault Tolerance: The Return of the 'Birthday Surprise'
IEEE Transactions on Computers
The Effect of Program Behavior on Fault Observability
IEEE Transactions on Computers
An empirical study of memory hardware errors in a server farm
HotDep'07 Proceedings of the 3rd workshop on on Hot Topics in System Dependability
Fault-Tolerant Memory Design and Partitioning Issues in Embryonics
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Reliability analysis of memories protected with BICS and a per-word parity bit
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A realistic evaluation of memory hardware errors and software system susceptibility
USENIXATC'10 Proceedings of the 2010 USENIX conference on USENIX annual technical conference
Fault Tolerant Single Error Correction Encoders
Journal of Electronic Testing: Theory and Applications
LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems
Proceedings of the 39th Annual International Symposium on Computer Architecture
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The lifetimes of computer memories which are protected with single-error-correcting-double-error-detecting (SEC-DED) codes are studies. The authors assume that there are five possible types of memory chip failure (single-cell, row, column, row-column and whole chip), and, after making a simplifying assumption (the Poisson assumption), have substantiated that experimentally. A simple closed-form expression is derived for the system reliability function. Using this formula and chip reliability data taken from published tables, it is possible to compute the mean time to failure for realistic memory systems.