A novel data processing circuit in high-speed serial communication
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On chip novel video streaming system for bi-network multicasting protocols
Integration, the VLSI Journal
Proceedings of the 48th Design Automation Conference
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From the Book:PREFACE: The MindShare Architecture Series The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley. Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other. Cautionary Note The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay. Specifications This Book is Based On This book is based on the Universal Serial Bus 2.0 specification. Organization of This Book The book is divided into sixpartsand contains the chapters listed below: Part I: Overview of USB 2.0 Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described. Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described. Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables. Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems. Part II: The USB Solution Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter. Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter. Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them. Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them. Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely. Part III: High Speed Device Operation Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment. Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation. Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter. Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect. Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions. Part IV: USB 2.0 Hub Operation with LS/FS/HS Devices Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports. Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub. Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each. Part V: USB Configuration Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed. Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed. Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports. Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio. Part VI: USB Software Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface. Who Should Read this Book This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful. Prerequisite Knowledge The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues. Visit Our Web Page Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, as well as course outlines. www.mindshare.com Our publisher's web page contains a listing or our currently-available books and includes pricing and ordering information. Their home page is accessible at: www.aw.com/cseng