Validating software pipelining optimizations

Authors:
Raya Leviathan;Amir Pnueli
Affiliations:
Weizmann Institute of Science;Weizmann Institute of Science
Venue:
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Year:
2002

Citing 8
Cited 8

Code generation schema for modulo scheduled loops

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Lifetime-sensitive modulo scheduling

PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Temporal verification of reactive systems: safety

Temporal verification of reactive systems: safety
Software pipelining

ACM Computing Surveys (CSUR)
Translation validation for an optimizing compiler

PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Data Refinement: Model-Oriented Proof Methods and Their Comparison

Data Refinement: Model-Oriented Proof Methods and Their Comparison
CVC: A Cooperating Validity Checker

CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Validation of Optimizing Compilers,

Validation of Optimizing Compilers,

Compiler verification: a bibliography

ACM SIGSOFT Software Engineering Notes
Refinement calculus: a basis for translation validation, debugging and certification

Theoretical Computer Science - Algebraic methods in language processing
Formal verification of translation validators: a case study on instruction scheduling optimizations

Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Code Graph Transformations for Verifiable Generation of SIMD-Parallel Assembly Code

Applications of Graph Transformations with Industrial Relevance
A simple, verified validator for software pipelining

Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Translation validation of loop optimizations and software pipelining in the TVOC framework: in memory of Amir Pnueli

SAS'10 Proceedings of the 17th international conference on Static analysis
Toward reliable and efficient message passing software through formal analysis

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Validating register allocation and spilling

CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction

Quantified Score

Hi-index	0.00

Visualization

Abstract

The paper presents a method for translation validation of a specific optimization, software pipelining optimization, used to increase the instruction level parallelism in EPIC type of architectures. Using a methodology as in [15] to establish simulation relation between source and target based on computational induction, we describe an algorithm that automatically produces a set of decidable proof obligations. The paper also describes SPV, a prototype translation validator that automatically produces verification conditions for software pipelining optimizations of the SGI Pro-64 compiler. These verification conditions are further checked automatically by the CVC [12] checker.