Architectural and Basic Circuit Considerations for a Flexible 128 × 128 Mixed-Signal SIMD Vision Chip

  • Authors:

  • G. Liñán;S. Espejo;R. Domínguez-Castro;A. Rodríguez-Vázquez

  • Affiliations:

  • Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012-Sevilla, Spain Tel.: +34 95 5056666, Fax: +34 95 5056686;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012-Sevilla, Spain Tel.: +34 95 5056666, Fax: +34 95 5056686;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012-Sevilla, Spain Tel.: +34 95 5056666, Fax: +34 95 5056686;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012-Sevilla, Spain Tel.: +34 95 5056666, Fax: +34 95 5056686

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2002

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Abstract

From a system level perspective, this paper presents a 128× 128 flexible and reconfigurable Focal-PlaneAnalog Programmable Array Processor,which has been designed as a single chip in a 0.35 µmstandard digital 1P-5M CMOS technology. The core processing arrayhas been designed to achieve high-speed of operation andlarge-enough accuracy (~7 bits) with low power consumption. Thechip includes on-chip program memory to allow for the execution ofcomplex, sequential and/or bifurcation flow image processingalgorithms. It also includes the structures and circuits needed toguarantee its embedding into conventional digital hosting systems:external data interchange and control are completely digital. Thechip contains close to four million transistors, 90% of themworking in analog mode. The chip features up to 330 GOPs(Giga Operations per second), and uses thepower supply (180 GOP/Joule) and the silicon area (3.8GOPS/mm2) efficiently, and is able to maintain VGAprocessing throughputs of 100 Frames/s with about 1020 basic imageprocessing tasks on each frame.