Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips

Authors:
A. Rodríguez-Vázquez;G. Liñán;S. Espejo;R. Domínguez-Castro
Affiliations:
Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012, Sevilla, Spain, Tel.: +34 95 5056666, Fax: +34 95 5056686. angel@imse.cnm.es;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012, Sevilla, Spain, Tel.: +34 95 5056666, Fax: +34 95 5056686;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012, Sevilla, Spain, Tel.: +34 95 5056666, Fax: +34 95 5056686;Instituto de Microelectrónica de Sevilla—CNM-CSIC, Edificio CICA-CNM, C/Tarfia s/n, 41012, Sevilla, Spain, Tel.: +34 95 5056666, Fax: +34 95 5056686
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2003

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Abstract

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range.The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.