Design and Power Optimization of High-Speed Pipeline ADCfor Wideband CDMA Applications

Authors:
Chunlei Shi;Yue Wu;Chi-Hung Lin;Mohammed Ismail
Affiliations:
The Analog VLSI Lab, Dept. of Electrical Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272 USA;The Analog VLSI Lab, Dept. of Electrical Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272 USA;The Analog VLSI Lab, Dept. of Electrical Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272 USA;The Analog VLSI Lab, Dept. of Electrical Engineering, The Ohio State University, 2015 Neil Avenue, Columbus, OH 43210-1272 USA
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2001

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Abstract

This paper presents a 7-bit 64 MS/s pipeline A/D convertersuitable for wideband CDMA applications. Targeting atachieving low power dissipation at high speed, techniques suchas digital correction and optimal scaling of capacitor valuehave been employed. Switched-Opamp technique is used tofurther reduce power consumption. This ADC is implemented in0.5 μm standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.