An 8-bit 40 MS/s Pipeline A/D Converter for WCDMA Testbed
Analog Integrated Circuits and Signal Processing - Selected papers from the NORCHIP '98 Conference
Design and Power Optimization of High-Speed Pipeline ADCfor Wideband CDMA Applications
Analog Integrated Circuits and Signal Processing
Adaptive CMOS analog circuits for 4G mobile terminals-Review and state-of-the-art survey
Microelectronics Journal
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This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures. The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm2. A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.