A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
System Level Tools for DSP in FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Analysis of the Execution Time Unpredictability caused by Dynamic Branch Prediction
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Wavelet kernels on a DSP: a comparison between lifting and filter banks for image coding
EURASIP Journal on Applied Signal Processing
Optimization of FIR filter implementation for FMT on VLIW DSP
CSS'10 Proceedings of the 4th international conference on Circuits, systems and signals
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Applications that use digital signal processing chips are flourishing, buoyed by increasing performance and falling prices. Concurrently, the market has expanded enormously. Vendors abound. Many newcomers have entered the market, while established companies compete for market share by creating ever more novel, efficient, and higher-performing architectures. The range of digital signal-processing (DSP) architectures available is unprecedented. In addition to expanding competition among DSP processor vendors, a new threat is coming from general-purpose processors with DSP enhancements. So, DSP vendors have begun to adapt their architectures to stave off the outsiders. The author provides a framework for understanding the recent developments in DSP processor architectures, including the increasing interchange of architectural techniques between DSPs and general-purpose processors