A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories

Authors:
Alistair A. McEwan;Jonathan Saul
Affiliations:
Oxford University Computing Laboratory, University of Oxford, U.K.alistair.mcewan@comlab.ox.ac.uk;Oxford University Computing Laboratory, University of Oxford, U.K.jonathan.saul@comlab.ox.ac.uk
Venue:
The Journal of Supercomputing
Year:
2001

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Abstract

A technique for implementing a Content Addressable Memory (CAM) on an FPGA is described. The CAM is highly parameterizable, allowing varying word widths, memory depths and operations to be implemented depending upon the requirements of the target application. The application of the CAM is then demonstrated by using it in the core of a network firewall application, where it is used in a pipeline IP packet detection algorithm. The firewall application is particularly useful in demonstrating the application potential of the CAM as the packet detection algorithm can be dynamically reconfigured to react to different criteria simply by altering the contents of the CAM. The result is a complete system on a chip.