Application of combined thermal and electrical simulation for optimization of deep submicron interconnection systems

Authors:
R. Streiter;H. Wolf;Z. Zhu;X. Xiao;T. Gessner
Affiliations:
Chemnitz University of Technology, Center of Microtechnologies, D-09107 Chemnitz, Germany;Fraunhofer Institute for Reliability and Microintegration, Department Micro Devices and Equipment, D-09126 Chemnitz, Germany;Fudan University, Department Electrical Engineering, CHN-2000433 Shanghai, China;Chemnitz University of Technology, Center of Microtechnologies, D-09107 Chemnitz, Germany;Chemnitz University of Technology, Center of Microtechnologies, D-09107 Chemnitz, Germany and Fraunhofer Institute for Reliability and Microintegration, Department Micro Devices and Equipment, D-0 ...
Venue:
Microelectronic Engineering
Year:
2002

Citing 2
Cited 0

A novel VLSI layout fabric for deep sub-micron applications

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Quantified Score

Hi-index	2.88

Visualization

Abstract

The thermal and the electrical behavior of interconnects for the 100 nm and the 50 nm technology node have been investigated with regard to the application of advanced dielectric materials. Their low thermal conductivity causes different design limitations for dc and ac carrying interconnects. The maximum possible current density of dc lines is determined by a self-consistent approach considering both Joule heating and electromigration (EM). The temperature of signal lines is related to the position-dependent current density. Temperature increase of less than 20 K is found near the front end of the interconnects. At high frequencies transient electrical behavior is strongly influenced by parasitic line capacitance and inductance. The effect on line temperature is simulated.