Advanced compiler design and implementation
Advanced compiler design and implementation
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Rematerialization-based register allocation through reverse computing
Proceedings of the 8th ACM International Conference on Computing Frontiers
International Journal of Parallel Programming
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A register-reuse chain is a set of nodes assigned to the same register. This paper proposes a systematic technique to generate register-reuse chains while aiming to reduce unnecessary dependencies. To avoid any dependency, the first phase of the proposed technique assigns two nodes to the same chain, only if the two nodes do not overlap their live ranges by any possible schedule. To reduce the number of chains, the second phase merges chains by assigning a node and one of its dependent nodes to the same chain. Evaluation shows that the proposed technique reduces dependencies by an average of 20.9%.