Decomposition of Convex Polygonal Morphological Structuring Elements into Neighborhood Subsets
IEEE Transactions on Pattern Analysis and Machine Intelligence
Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A Heterogeneous Multiprocessor Architecture for Low-Power Audio Signal Processing Applications
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Rapid prototyping for mixed architectures
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A reconfigurable 8 GOP ASIC architecture for high-speed data communications
IEEE Journal on Selected Areas in Communications
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The aim of this work is the achievement of a rapid prototyping process for the implementation of digital image processing applications on mixed and parallel architectures. The target platforms are made up of one multi-DSP part (software) and FPGA (dedicated hardware). This prototyping process includes the SynDEx tool as a low level tool to generate an optimized and distributed executive according to the platform. We propose to use as front-end tool a higher-level environment, Ptolemy, dedicated to the functional visualization and verification of signal or image-processing applications. An automatic translator is created to constitute the link between Ptolemy and SynDEx removing henceforth the manual translation stage. As a result, a signal-processing designer develops complex applications at a high level and can put the implementation on a complex architecture without any hardware pre-requirements. The prototyping process becomes fast and secured and the digital image-processing designer manages the whole development process and can easily achieve possible modifications. Currently ARIAL is a unique automatic prototyping process, which uses a functional description, for the implementation of applications on a multi-DSP + FPGA architecture.