ARIAL: rapid prototyping for mixed and parallel platforms
Parallel Computing - Parallel computing in image and video processing
Sub µW noise reduction for CIC hearing aids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multi-processor consisting of small and simple instruction set processors called mini-cores that communicate using message passing. The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occur at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word x 16 bit program memory, a 64 word x 16 bit data memory and a 25 word x 16 bit coefficient memory. Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSP's implemented using full-custom techniques. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.