Operations research: an introduction, 4th ed.
Operations research: an introduction, 4th ed.
Modern FPGA constrained placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An integer programming placement approach to FPGA clock power reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer linear programming formulation for the constrained I/O placement problem. The size of the integer linear program derived is independent of the number of I/O objects to be placed and hence is scalable to very large design instances. For example, for a Xilinx Virtex-E FPGA, the number of integer variables required is never more than 32 and is much smaller for practical design instances. Extensive experimental results using a non-commercial integer linear program solver shows that it only takes seconds to solve the resultant integer linear program in practice.