A graphics system architecture for interactive application-specific display functions
IEEE Computer Graphics and Applications
MPEG: a video compression standard for multimedia applications
Communications of the ACM - Special issue on digital multimedia systems
Multimedia electronic mail: will the dream become a reality?
Communications of the ACM - Special issue on digital multimedia systems
A scalable hardware render accelerator using a modified scanline algorithm
SIGGRAPH '92 Proceedings of the 19th annual conference on Computer graphics and interactive techniques
High-performance polygon rendering
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A display system for the Stellar graphics supercomputer model GS1000
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
Efficient address remapping in distributed shared-memory systems
ACM Transactions on Architecture and Code Optimization (TACO)
Scalable barrier synchronisation for large-scale shared-memory multiprocessors
International Journal of High Performance Computing and Networking
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This paper describes a programmable pixel processor, the SX, that has been implemented in the memory controller chip of a workstation. The goal of the SX is to achieve performance comparable to that of low end 2D and 3D graphics processors and to surpass low-end imaging accelerators, at the lowest possible cost. The SX is an integer vector processor, with an instruction set tailored to the needs of image processing and multimedia as well as 2D and 3D graphics. It can directly access data in both video and main memory, allowing accelerated processing on images up to about 400 megabytes in size. The SX offers a cost-effective method of providing graphics and image processing capability compared to traditional workstation and accelerator approaches.