LUCAS associative array processor: design, programming and application studies
LUCAS associative array processor: design, programming and application studies
Self-organization and associative memory: 3rd edition
Self-organization and associative memory: 3rd edition
The DARPA image understanding benchmark for parallel computers
Journal of Parallel and Distributed Computing
Computer vision application with the associative string processor
Journal of Parallel and Distributed Computing
Associative and Parallel Processors
ACM Computing Surveys (CSUR)
Associative Processor Architecture—a Survey
ACM Computing Surveys (CSUR)
Associative Computing: A Programming Paradigm for Massively Parallel Computers
Associative Computing: A Programming Paradigm for Massively Parallel Computers
Contentaddressable Memories
Content Addressable Parallel Processors
Content Addressable Parallel Processors
Parallel Models of Associative Memory
Parallel Models of Associative Memory
ASP: A Cost-Effective Parallel Microcomputer
IEEE Micro
Distributed flow detection over multi path sessions
Proceedings of the 4th international conference on Security and privacy in communication netowrks
A Semantic Space Creation Method with an Adaptive Axis Adjustment Mechanism for Media Data Retrieval
Proceedings of the 2008 conference on Information Modelling and Knowledge Bases XIX
A Semantic Spectrum Analyzer for Realizing Semantic Learning in a Semantic Associative Search Space
Proceedings of the 2006 conference on Information Modelling and Knowledge Bases XVII
Proceedings of the 2007 conference on Information Modelling and Knowledge Bases XVIII
A note on architectures for large-capacity CAMs
Integration, the VLSI Journal
Distributed flow detection over multi-path sessions
Computer Communications
Emotions: the voice of the unconscious
ICEC'10 Proceedings of the 9th international conference on Entertainment computing
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Associative memory concerns the concept that one idea may trigger the recall of a different but related idea. Traditional computers, however, rely upon a memory design that stores and retrieves data by its address rather than its content. In such a search, every accessed data word must travel individually between the processing unit and the memory. The simplicity of this retrieval-by-address approach has ensured its success, but has also produced some inherent disadvantages. One is the von Neumann bottleneck, where the memory-access path becomes the limiting factor for system performance. A related disadvantage is the inability to proportionally increase the size of a unit transfer between the memory and the processor as the size of the memory scales up. Associative memory, in contrast, provides a naturally parallel and scalable form of data retrieval for both structured data (e.g. sets, arrays, tables, trees and graphs) and unstructured data (raw text and digitized signals). An associative memory can be easily extended to process the retrieved data in place, thus becoming an associative processor. This extension is merely the capability for writing a value in parallel into selected cells.