Experience acquiring and retargeting a portable Ada computer
Software—Practice & Experience
Hardware support for efficient execution of Ada tasking
Proceedings of the Twenty-First Annual Hawaii International Conference on Architecture Track
A real-time support processor for ada tasking
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The performance of a prototype coprocessor for Ada tasking
TRI-Ada '90 Proceedings of the conference on TRI-ADA '90
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
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A VLSI coprocessor that radically improves the real-time performance of the Ada tasking model, especially the rendezvous, is discussed. An overview of multilevel design is given, and design levels and models are examined. A description is given of the design strategy, which entails stepwise refinement of functional models representing the coprocessor at more and more detailed levels. A chip was generated using the Genesil silicon compiler, but most of the design was defined and verified on the instruction-set-processor and register-transfer levels.