Toward real-time performance benchmarks for Ada
Communications of the ACM
Experience acquiring and retargeting a portable Ada computer
Software—Practice & Experience
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
A microprocessor with Ada real time support
TRI-Ada '91 Proceedings of the conference on TRI-Ada '91: today's accomplishments; tomorrow's expectations
The performance of a prototype coprocessor for Ada tasking
TRI-Ada '90 Proceedings of the conference on TRI-ADA '90
Termination of Ada tasks in hardware
Proceedings of the conference on TRI-Ada '95: Ada's role in global markets: solutions for a changing complex world
Designing a Real-Time Coprocessor for Ada Tasking
IEEE Design & Test
Using hardware support for scheduling with ada
Ada-Europe'10 Proceedings of the 15th Ada-Europe international conference on Reliable Software Technologies
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Task synchronization in Ada causes excessive run-time overhead due to the complex semantics of the rendezvous. To demonstrate that the speed can be increased by two orders of magnitude by using special purpose hardware, a single chip VLSI support processor has been designed. By providing predictable and uniformly low overhead for the entire semantics of a rendezvous, the powerful real-time constructs of Ada can be used freely without performance degradation.The key to high performance is the set of primitive operations implemented in hardware. Each operation is complex enough to replace a considerable amount of code was designed to execute with a minimum of communication overhead. Task control blocks are stored on-chip as well as headers for entry, delay and ready queues. All necessary scheduling is integrated in the operations. Delays are handled completely on-chip using an internal real-time clock.A multilevel design strategy, based on silicon compilation, made it possible to run actual Ada programs on a functional emulator of the chip and use the results to verify the detailed design. A high degree of parallelism and pipelining together with an elaborate internal addressing scheme has reduced the number of clock cycles needed to perform each operation. Using 2 &mgr;m CMOS, the processor can run at 20 MHz. A complex rendezvous, including the calling sequence and all necessary scheduling, can be performed in less than 15 &mgr;s.