Processor architecture and cache performance
Processor architecture and cache performance
A real-time support processor for ada tasking
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Naming and Binding in a Vertical Migration Environment
IEEE Transactions on Software Engineering
Transparent microprogramming in support of abstract type oriented dynamic vertical migration
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Custom-fit processors: letting applications define architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A framework for high-speed controller design
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Automated design of finite state machine predictors for customized processors
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Paper: A boltzmann machine approach to code optimization
Parallel Computing
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ASIC microprocessors are becoming an important technology for the control of complex (“embedded”) systems. The advantage of such microprocessors is that they can be tailored to the application. This tailoring is quite non-intuitive and optimization is a complex process. Tools such as the Architect's Workbench (AWB) have been developed to assist in this optimization. An example study shows a more than two to one advantage of such assisted analysis.