Multi-level simulation for VLSI design
Multi-level simulation for VLSI design
From objects to classes: algorithms for optimal objection-oriented design
Software Engineering Journal
Communications of the ACM
Digital Design with VERILOG HDL
Digital Design with VERILOG HDL
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
CONLAN Report
The conlan project: Status and future plans
DAC '82 Proceedings of the 19th Design Automation Conference
SABLE: A tool for generating structured, multi-level simulations
DAC '79 Proceedings of the 16th Design Automation Conference
The Evolution of SystemVerilog
IEEE Design & Test
Aspect-oriented design in systemC: implementation and applications
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
| Hi-index | 0.00 |
For pt.1 see ibid., June 1992. Current hardware description languages (HDLs) benefit from the efforts of designers of VHDLs in the mid-1970s through the late 1980s. The developers of four HDLs discuss their motivations and their views of how their work relates to the present very-high-speed integrated circuit HDLs (VHDLs). The languages discussed are Conlan, ADLIB/SABLE, Zeus, and Verilog.