A mapping algorithm for computer-assisted exploration in the design of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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A system design to physical design methodology based on developing and integrating reusable "cores" was used to develop a complex 0.5-micron digital QAM demodulator/FEC decoder. This highly automated design flow encapsulates ESDA tools, logic synthesis and standard cell place and route tools into a Make/RCS environment that simplifies design complexity management and brings in physical design information early in the design cycle. This methodology enables a new style of design team organization in which each designer is responsible for all aspects of core development, from system level architecture through place and route and post-layout timing verification. This methodology facilitates design re-use and greatly reduces the cycle time of complex deep submicron designs.