The i860TM 64-bit supercomputing microprocessor
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
A timed Petri-net model for fine-grain loop scheduling
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
The Intel i860 64-Bit Processor: A General-Purpose CPU with 3D Graphics Capabilities
IEEE Computer Graphics and Applications
Performance and the i860 Microprocessor
IEEE Micro
A timed Petri-net model for fine-grain loop scheduling
CASCON '91 Proceedings of the 1991 conference of the Centre for Advanced Studies on Collaborative research
A new perspective for efficient virtual-cache coherence
Proceedings of the 40th Annual International Symposium on Computer Architecture
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The authors describe the single-chip i860 CPU, a 64-bit, RISC (reduced-instruction-set-computer)-based microprocessor that executes parallel instructions using mainframe and supercomputer architectural concepts. They designed the 1,000,000-transistor, 10-mm*15-mm processor for balanced integer, floating-point, and graphics performance. They discuss the RISC core, memory management, floating-point unit, graphics, bus interface, software support, and interfacing to a DRAM system