Communications of the ACM - Special section on computer architecture
A Characterization and Analysis of Parallel Processor Interconnection Networks
IEEE Transactions on Computers
SIGCSE '85 Proceedings of the sixteenth SIGCSE technical symposium on Computer science education
Sixteen Bit Microprocessor Handbook
Sixteen Bit Microprocessor Handbook
Kestrel: A Programmable Array for Sequence Analysis
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Extended Hypercube: A Hierarchical Interconnection Network of Hypercubes
IEEE Transactions on Parallel and Distributed Systems
Kestrel: Design of an 8-bit SIMD Parallel Processor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
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An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use intermediate buffers, input/output ports, or DMAs. The example of a three-dimensional cube is used to illustrate the advantages of this scheme. The implementation of the interprocessor communication scheme on a 64-node cube configuration is discussed