A new string search hardware architecture for VLSI
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Practical minimal perfect hash functions for large databases
Communications of the ACM
The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Communications of the ACM
Contentaddressable Memories
IEEE/ACM Transactions on Networking (TON)
A keyword match processor architecture using content addressable memory
Proceedings of the 14th ACM Great Lakes symposium on VLSI
FPGA based string matching for network processing applications
Microprocessors & Microsystems
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The various methods of connecting multiple content-addressable memory (CAM) devices to form a memory system of larger dimensions are surveyed. They include daisy-chaining CAMs to increase the number of elements and possibly using carry-lookahead logic to increase the cascade. To increase the data size, one can replicate the labels in distinct CAMs, use the data storage available in a primary CAM to index a secondary CAM/RAM (read-only memory), or reduce redundancy in labels. To increase the label size, one can use an element cascade with or without a shift register, a master-slave cascade, or a trie cascade. One of the methods examined for increasing the label size is a new trie cascade approach.