Cached DRAM for ILP Processor Memory Access Latency Reduction

Authors:
Zhao Zhang;Zhichun Zhu;Xiaodong Zhang
Affiliations:
-;-;-
Venue:
IEEE Micro
Year:
2001

Citing 7
Cited 8

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Abstract

Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced dram techniques for reducing memory access latency in instruction-level-parallelism processors.