Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
A comparative study of unification algorithms for or-parallel execution of logic languages
IEEE Transactions on Computers
The C programming language
A new parallel inference mechanism based on sequential processing
Proc. of the IFIP TC 10 working conference on Fifth generation computer architectures
OR-Parallel execution of prolog on a multi-sequential machine
International Journal of Parallel Programming
Principles of the Delphi parallel inference machine
The Computer Journal
Concurrent prolog: collected papers
Concurrent prolog: collected papers
High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)
IEEE Transactions on Computers
The muse approach to Or-parallel Prolog
International Journal of Parallel Programming
Performance studies of a Prolog machine architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Logic for Problem Solving
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Parallel interpretation of logic programs
FPCA '81 Proceedings of the 1981 conference on Functional programming languages and computer architecture
International Journal of Computational Science and Engineering
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An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a trace-driven simulation study. This inference machine consists of a large number of processing elements (PEs) with serial I/O links directly connected to each other in a simply modified mesh network. Each PE is a high-speed sequential Prolog processor with its own local memory. The activity of all PEs is locally controlled by four new load balancing algorithms based on purely local communication. Communication is allowed only between directly connected PEs. These load balancing algorithms reduce communication overhead in a load balancing and make it possible to accomplish highly OR-parallel execution. A software simulator using a trace-driven simulation technique based on an inference tree has been developed, and some typical OR-parallel benchmarks such as the n-queens problem have been simulated on it. The average communication per load balancing is reduced by a factor ranging from 1/30 to 1/100 by the interaction of these load balancing algorithms as compared with a conventional copying method. The inference machine (1024 PEs; 32/spl times/32 array) attains 300-600 times parallel speedup, assuming 1 MLIPS (mega logical inferences per second) PE and a 20 MBPS (mega bits per second) each serial I/O link, which could be easily integrated on a single chip using current VLSI technology. This highly OR-parallel inference machine promises to be an important step towards the realization of a high-performance artificial intelligence system.