Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Dynamic fault tolerance in DCMA-a dynamically configurable multicomputer architecture
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
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We propose the dynamic reconfiguration network (DRN) and a monitoring-at-transmission (MAT) bus to support dynamic reconfiguration of an N-modular redundancy (NMR) multiprocessor system. In the reconfiguration process, a maximal number of processor triads are guaranteed to be formed on each processor cluster, thus supporting gracefully degradable operations. This is made possible by dynamically routing the control and clock signals of processors on the DRN so as to synchronize fault-free processors. The MAT bus is an efficient way to implement a triple modular redundant (TMR) pipeline voter (PV), which is a special case of the voting network proposed in [1]. Extensive experimental results have shown to support our design concept, and the performance of different cache memory organizations is evaluated through an analytic model.