Hypernet: A communication-efficient architecture for constructing massively parallel computers
IEEE Transactions on Computers
IEEE Transactions on Computers
The Twisted N-Cube with Application to Multiprocessing
IEEE Transactions on Computers
A Variation on the Hypercube with Lower Diameter
IEEE Transactions on Computers
RH: A Versatile Family of Reduced Hypercube Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Properties and Performance of Folded Hypercubes
IEEE Transactions on Parallel and Distributed Systems
Extended Hypercube: A Hierarchical Interconnection Network of Hypercubes
IEEE Transactions on Parallel and Distributed Systems
Algorithms and Properties of a New Two-Level Network with Folded Hypercubes as Basic Modules
IEEE Transactions on Parallel and Distributed Systems
Rapid Prototyping of Parallel Processing Systems on TESH Network
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Reconfigurable tesh connected parallel computers
Reconfigurable tesh connected parallel computers
VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper considers defect tolerance issues for parallel computing systems based on a new interconnection network, namely "Tori connected mESHes (TESH)." Key features of this network are the following: It is hierarchical, thus allowing exploitation of computation locality and systematic expansion up to a million processors, and it appears to be well-suited for VLSI/ULSI realization, including 3D implementation. The goal here is to present efficient reconfiguration algorithms for such hierarchical parallel computing systems. Despite the dramatic improvement in defect density in recent years, it is still necessary to provide redundancy and defect circumvention to achieve acceptable system-level yields for large multicomputer systems. The TESH-based parallel systems are no exception. Therefore, we develop placement and routing algorithms that assign logical nodes to healthy physical nodes and configure switches to bypass the defective cells, switches, and links. Simulations indicate that the placement (or remapping) is nearly 100 percent effective, while the routing performance diminishes with increasing defect density for a given extent of redundancy. The approach scales up well because, in TESH networks, essentially the same kind of sparing is used at all levels.