The performance analysis of partitioned circuit switched multistage interconnection networks
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
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ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A Markov-modulated Bernoulli process approximation for the analysis of Banyan Networks
SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
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IEEE Transactions on Computers
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The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n/sup 2/+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained.