A parallel-design distributed-implementation (PDDI) general-purpose computer
Theoretical Computer Science
Type architectures, shared memory, and the corollary of modest potential
Annual review of computer science vol. 1, 1986
Deterministic simulation of idealized parallel computers on more realistic ones
SIAM Journal on Computing
Parallel complexity theory
Efficient parallel algorithms
The design and analysis of parallel algorithms
The design and analysis of parallel algorithms
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
Vector models for data-parallel computing
Vector models for data-parallel computing
Journal of Computer and System Sciences
Parallel algorithms for shared-memory machines
Handbook of theoretical computer science (vol. A)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel General Prefix Computations with Geometric, Algebraic and Other Applications
FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
Bounds on the time for parallel RAM's to compute simple functions
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Computational Aspects of VLSI
IEEE Transactions on Parallel and Distributed Systems
An Efficient Implementation for the BROADCAST Instruction of BSR+
IEEE Transactions on Parallel and Distributed Systems
On Time Bounds, the Work-Time Scheduling Principle, and Optimality for BSR
IEEE Transactions on Parallel and Distributed Systems
Optimal BSR Solutions to Several Convex Polygon Problems
The Journal of Supercomputing
Work-efficient BSR-based parallel algorithms for some fundamental problems in graph theory
The Journal of Supercomputing
Towards efficient BSP implementations of BSR programs for some computational geometry problems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
O(1) time algorithm on BSR for constructing a binary search tree with best frequencies
PDCAT'04 Proceedings of the 5th international conference on Parallel and Distributed Computing: applications and Technologies
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A model of parallel computation called broadcasting with selective reduction (BSR) can be viewed as a concurrent-read concurrent-write (CRCW) parallel random access machine (PRAM) with one extension. An additional type of concurrent memory access is permitted in BSR, namely the BROADCAST instruction by means of which all N processors may gain access to all M memory locations simultaneously for the purpose of writing. At each memory location, a subset of the incoming broadcast data is selected and reduced to one value finally stored in that location. For several problems, BSR algorithms are known which require fewer steps than the corresponding best-known PRAM algorithms, using the same number of processors. A circuit is introduced to implement the BSR model, and it is shown that, in size and depth, the circuit presented is of the same order as an optimal circuit implementing the PRAM. Thus, if it is reasonable to assume that CRCW PRAM instructions execute in constant time, the assumption of a constant time BROADCAST instruction is no less reasonable.