A Formal Definition of Data Flow Graph Models
IEEE Transactions on Computers
Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
The effect of operation scheduling on the performance of a data flow computer
IEEE Transactions on Computers
Preemptive scheduling under time and resource constraints
IEEE Transactions on Computers - Special Issue on Real-Time Systems
Performance modeling and enhancement for the ATAMM data flow architecture
Performance modeling and enhancement for the ATAMM data flow architecture
Scheduling algorithms for hard real-time systems: a brief survey
Tutorial: hard real-time systems
Scheduling Periodic Jobs that Allow Imprecise Results
IEEE Transactions on Computers
Guest Editor's Introduction: Distributed Computing Systems
Computer - Distributed computing systems: separate resources acting as one
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration
IEEE Transactions on Computers
MILP based task mapping for heterogeneous multiprocessor systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Performance analysis for parallel solutions to generic search problems
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Performance modeling and analysis of correlated parallel computations
Parallel Computing
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Presents a new data flow graph model for describing the real-time execution of iterativecontrol and signal processing algorithms on multiprocessor data flow architectures.Identified by the acronym ATAMM, for Algorithm to Architecture Mapping Model, themodel is important because it specifies criteria for a multiprocessor operating system toachieve predictable and reliable performance. Algorithm performance is characterized byexecution time and iteration period. For a given data flow graph representation, the modelfacilitates calculation of greatest lower bounds for these performance measures. Whensufficient processors are available, the system executes algorithms with minimumexecution time and minimum iteration period, and the number of processors required iscalculated. When only limited processors are available or when processors fail,performance is made to degrade gracefully and predictably. The user off-line is able tospecify tradeoffs between increasing execution time or increasing iteration period. The approach to achieving predictable performance is to control the injection rate of inputdata and to modify the data flow graph precedence relations so that a processor isalways available to execute an enabled graph node. An implementation of the ATAMMmodel in a four-processor architecture based on Westinghouse's VHSIC 1750A Instruction Set Processor is described.