Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
A hypercube algorithm for the 0/1 knapsack problem
Journal of Parallel and Distributed Computing
Parallel branch-and-bound algorithm
Future Generation Computer Systems
Adaptive parallel algorithms for integral knapsack problems
Journal of Parallel and Distributed Computing - Special issue: algorithms for hypercube computers
Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
Introduction to parallel computing: design and analysis of algorithms
Introduction to parallel computing: design and analysis of algorithms
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
Anomalies in parallel branch-and-bound algorithms
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems
ICCI '91 Proceedings of the International Conference on Computing and Information: Advances in Computing and Information
Efficient Linear Systolic Array for the Knapsack Problem
CONPAR '92/ VAPP V Proceedings of the Second Joint International Conference on Vector and Parallel Processing: Parallel Processing
Dynamic Programming
Solving Bi-knapsack Problem Using Tiling Approach for Dynamic Programming
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
An efficient parallel algorithm for solving the Knapsack problem on hypercubes
Journal of Parallel and Distributed Computing
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We present a parallel solution to the unbounded knapsack problem on a linear systolic array. It achieves optimal speedup for this well-known, NP-hard problem on a model of computation that is weaker than the PRAM. Our array is correct by construction, as it is formally derived by transforming a recurrence equation specifying the algorithm.This recurrence has dynamic dependencies, a property that puts it beyond the scope of previous methods for automatic systolic synthesis. Our derivation thus serves as a case study. We generalize the technique and propose a systematic method for deriving systolic arrays by nonlinear transformations of recurrences. We give sufficient conditions that the transformations must satisfy, thus extending systolic synthesis methods.We address a number of pragmatic considerations: implementing the array on only a fixed number of PEs, simplifying the control to just two counters and a few latches, and loading the coefficients so that successive problems can be pipelined without any loss of throughput.Using a register level model of VLSI, we formulate a nonlinear optimization problem to minimize the expected running time of the array. The analytical solution of this problem allows us to choose the memory size of each PE in an optimal manner.