Microprocessor interfacing and the 68000 peripherals and systems
Microprocessor interfacing and the 68000 peripherals and systems
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Tutorial on message sequence charts
Computer Networks and ISDN Systems - Special issue on SDL and MSC
VHDL generation from SDL specifications
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Notes on SDL-2000 for the new millennium
Computer Networks: The International Journal of Computer and Telecommunications Networking - special issue on MSC and SDL in project life cycles
MSC-2000 interaction diagrams for the new millennium
Computer Networks: The International Journal of Computer and Telecommunications Networking - special issue on MSC and SDL in project life cycles
Introduction to Digital Logic Design
Introduction to Digital Logic Design
Concurrent Specification and Timing Analysis of Digital Hardware Using SDL
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Modelling Digital Logic in SDL
FORTE X / PSTV XVII '97 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE X) and Protocol Specification, Testing and Verification (PSTV XVII)
An approach to Verilog-VHDL interoperability for synchronous designs
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Hi-index | 0.00 |
Specification and Description Language (SDL) is a standardised formal description technique for telecommunications software. ObjectGEODE is a commercial toolset which supports software design using SDL. This article presents a way of using SDL and ObjectGEODE to write formal specifications of synchronous sequential circuits quickly and to automatically verify their functional correctness. The circuits are treated as binary-encoded finite-state machines with local variables representing internal combinational wires. Typical circuit components, such as logic gates, structural combinational circuits, and flip-flops, are specified by SDL operators. Components of the same type but with a different number of inputs and/or outputs can be specified by one general SDL operator. The GOAL language supported by ObjectGEODE is shown to be appropriate for circuit verification.