Concurrent Specification and Timing Analysis of Digital Hardware Using SDL

  • Authors:

  • Kenneth J. Turner;F. Javier Argul-Marin;Stephen D. Laing

  • Affiliations:

  • -;-;-

  • Venue:
  • IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
  • Year:
  • 2000

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    Computer Communications - Special issue on practical use of FDTs in communications & distributed systems

  • VHDL generation from SDL specifications

    CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems

  • Modelling Digital Logic in SDL

    FORTE X / PSTV XVII '97 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE X) and Protocol Specification, Testing and Verification (PSTV XVII)

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Abstract

Digital hardware is treated as a collection of interacting parallel components. The ANISEED method (Analysis In SDL Enhancing Electronic Design) uses SDL (Specification and Description Language) to specify and analyse timing characteristics of hardware designs. A library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces.