The reconfigurable arithmetic processor

Authors:
S. Fiske;W. J. Dally
Affiliations:
Massachusetts Institute of Technolgy, Cambridge, MA;Massachusetts Institute of Technology, Cambridge, MA
Venue:
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Year:
1988

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Abstract

The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. It incorporates on one chip several serial, 64 bit floating point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units the RAP reduces the amount of off chip data transfer: in the examples we have simulated off chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. Simulations predict a peak performance of 20M Flops with 800Mbit/sec off chip bandwidth in a 2&mgr;m CMOS process.