A cache-based message passing scheme for a shared-bus multiprocessor

Authors:
B. R. Preiss;V. C. Hamacher
Affiliations:
Univ. of Waterloo, Waterloo, Ont., Canada;Univ. of Toronto, Toronto, Ont., Canada
Venue:
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Year:
1988

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Abstract

This paper describes a scheme for using cache-based hardware to provide simple and efficient message passing support for message-based software systems on a tightly-coupled, shared-bus multiprocessor. This approach is based on the utilization of the existing interprocessor communications medium, the shared bus, to effect the exchange of single-word messages. Communication between processes is accomplished over logical channels using simple, blocking send and receive primitives. The physical processor/channel interface is designed so that the message transfer primitives can be implemented as single machine instructions, namely store and fetch. Special-purpose caches, called message caches, mediate channel operations and effect the exchange of messages over the shared bus.