A general class of processor interconnection strategies
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Towards automated design of multicomputer system for real-time applications (architecture, task division)
Matrix operations on a multicomputer system with switchable main memory modules and dynamic control
IEEE Transactions on Computers
Modeling of parallel software for efficient computation communication overlap
ACM '87 Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Providing a cloud network infrastructure on a supercomputer
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing
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A 24 node multiprocessor computer system is currently under development at the N. C. State University. A diameter oriented ALPHA structure is used for interconnecting the computers which will operate in a MIMD mode. A communications processor is added to each node to satisfy data communications requirements in an efficient manner in a packet switched environment. A host computer will be used for program development and compilation. The software complexity will be reduced by the use of a static mapping of the partitioned computational flow diagram representing the algorithm to be executed. The long range goal of this research project is to develop a hierarchical structure with each node being replaced by a cluster of simple processors which are custom designed to implement computational primitives associated with digital signal and image processing applications.