Introduction to algorithms
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The predictability of data values
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Can program profiling support value prediction?
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The effect of instruction fetch bandwidth on value prediction
Proceedings of the 25th annual international symposium on Computer architecture
Value speculation scheduling for high performance processors
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Value prediction in VLIW machines
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Compiler controlled value prediction using branch predictor based confidence
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Focusing processor policies via critical-path prediction
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Available Parallelism with Data Value Prediction
HIPC '98 Proceedings of the Fifth International Conference on High Performance Computing
Treegion Scheduling for Wide Issue Processors
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Dynamic Prediction of Critical Path Instructions
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Compiler-driven value speculation scheduling
Compiler-driven value speculation scheduling
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Hi-index | 14.98 |
Techniques for value speculation have been proposed for dynamically scheduled and statically scheduled machines to increase instruction-level parallelism (ILP) by breaking flow (true) dependences and allowing value-dependent operations to be executed speculatively. The effectiveness of value speculation depends upon the ability to select and break dependences to shorten overall execution time, while encountering penalties for value misprediction. To understand and improve the techniques for value speculation, we model value speculation as an optimal edge selection problem. The optimal edge selection problem involves finding a minimal set of edges (dependences) to break in a data dependence graph that achieves maximal benefits from value speculation, while taking the penalties for value misprediction into account. Based on three properties observed from the optimal edge selection problem, an efficient optimal edge selection algorithm is designed. From the experimental results of running the optimal edge selection algorithm for the 20 most heavily executed paths selected from each SPECint95 benchmark, several insights are shown. The average critical path reduction is 9.61 percent on an average and 25.57 percent at its maximum. Surprisingly, 66 percent of the edges selected by the optimal algorithm have value prediction accuracies over 99 percent. Moreover, most of the selected edges cross the middle of the data dependence graph. The selected producer operations thereby tend to reside in the upper portion of the data dependence graph, while the selected consumer operations appear toward the lower portion.