Modeling concepts for VLSI CAD objects
ACM Transactions on Database Systems (TODS)
RCS—a system for version control
Software—Practice & Experience
An editor for revision control
ACM Transactions on Programming Languages and Systems (TOPLAS)
Maintaining Configurations of Evolving Software Systems
IEEE Transactions on Software Engineering
IEEE Transactions on Software Engineering
Version Support for Engineering Database Systems
IEEE Transactions on Software Engineering
Representability of design objects by ancestor-controlled hierarchical specifications
PODS '90 Proceedings of the ninth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems
Minimizing time-space cost for database version control
Proceedings of the seventh ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems
Differential files: their application to the maintenance of large databases
ACM Transactions on Database Systems (TODS)
A technique for isolating differences between files
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A database approach for managing VLSI design data
DAC '82 Proceedings of the 19th Design Automation Conference
Two linear-time algorithms for five-coloring a planar graph
Two linear-time algorithms for five-coloring a planar graph
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A paradigm is proposed for representing hierarchically specified design data in CAD database systems in which there are alternate expansions of hierarchically specified modules. The paradigm uses an ancestor-based scheme to control which instances of submodules are to be placed in the expansion of each instance of a given module and is formalized using a versioned directed acyclic multigraph (VDAG). The approach is aimed at reducing storage space in engineering design database systems and at providing a means for designers to specify alternate expansions of a module. The VDAG model is defined, and a mechanism by which a VDAG generates an exploded forest of design trees is described. Algorithms are provided to generate a design forest from a given VDAG, determine whether one module is contained by a larger module, extract a version from a VDAG, test whether two VDAGs are equivalent, and try to reduce the size of a VDAG. The problems of module containment and VDAG inequivalence are shown to be NP-complete, and the problem of finding a minimum sized VDAG equivalent to a given VDAG is shown to be NP-hard.