The effect of speculatively updating branch history on branch prediction accuracy, revisited
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Multiple-block ahead branch predictors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The potential of data value speculation to boost ILP
ICS '98 Proceedings of the 12th international conference on Supercomputing
Modeling program predictability
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Using value prediction to increase the power of speculative execution hardware
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Correlated load-address predictors
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Using Dataflow Based Context for Accurate Value Prediction
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Global Context-Based Value Prediction
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PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
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Recent work has shown that the hurdles imposed by data dependences on parallelism can be overcome to some extent with the use of data value prediction. This paper highlights how data value history is affected when implementing data value predictors in fine-grained parallel processors, wherein microarchitectural issues affect the recorded history. Simulation studies show that mispredictions increase and correct predictions decrease when the recorded history is not updated properly. The paper also investigates techniques for overcoming the effects of value history disruption. The investigated techniques rely on extrapolation of outdated history so as to make it up-to-date, and utilization of misprediction information to turn off predictions of subsequent instances of the mispredicted instruction. We evaluate the proposed techniques using a cycle-accurate simulator for a superscalar processor. Results from this study indicate that the extrapolation technique is indeed able to provide up-to-date history in most of the cases, and is able to recoup most of the ground lost due to microarchitectural effects. Utilization of misprediction information helps to further reduce the number of mispredictions, although in some cases it reduces the number of correct predictions also.