Two-dimensional round-robin schedulers for packet switches with multiple input queues
IEEE/ACM Transactions on Networking (TON)
A quantitive comparision of iterative scheduling algoithm for input-queued switches
Computer Networks and ISDN Systems
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Scalable Scheduling Support for Loss and Delay Constrained Media Streams
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Switch Scheduling in the Multimedia Router (MMR)
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
A two-stage hardware scheduler combining greedy and optimal scheduling
Journal of Parallel and Distributed Computing
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The primary objective of the Multimedia Router (MMR) [1] project is to design and implement a single chip router targeted for use in cluster and LAN interconnection networks. The goal can be concisely captured in the phrase 'QoS routing at link speeds'. This paper studies a set of algorithms for switch scheduling based on a highly concurrent implementation for capturing output port requests. Two different switch-scheduling algorithms called Row-Column Ordering and Diagonal Ordering are proposed and implemented in a switch-scheduling framework which involves a matrix data structure, and therefore enables concurrent and parallel operations at high-speed. Their performance has been evaluated with Constant Bit Rate (CBR), Variable Bit Rate (VBR), and a mixture of CBR and VBR traffic. At high offered loads both these ordering functions have been shown to deliver superior Quality of Service (QoS) to connections at a high scheduling rate and high utilization.