Architecture and design of a 40 gigabit per second ATM switch

Authors:
Steven E. Butner;David A. Skirmont
Affiliations:
-;-
Venue:
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Year:
1995

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Abstract

This paper presents the architecture of a very high performance 4-input, 4-output asynchronous transfer mode (ATM) switch that has been designed as part of the ARPA-sponsored "Thunder and Lightning" project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and switches operating at or above 40 gigabits per second per TDM link, with potential scalability to 100 Gbps. Such aggressive link rates place severe requirements on switch architecture, particularly the buffering scheme. In this paper we present the ATM switch structure and justify the main design choices.