Redundant Arithmetic Optimizations (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Journal of Systems Architecture: the EUROMICRO Journal
Asymmetrically banked value-aware register files for low-energy and high-performance
Microprocessors & Microsystems
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Exploiting narrow-width values for thermal-aware register file designs
Proceedings of the Conference on Design, Automation and Test in Europe
On the exploitation of narrow-width values for improving register file reliability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an integrated adder/subtracter/zero-detector in which the zero detection completes well before the sum or difference is known. Previous zero detectors either required the sum to be available before they could complete, or were not well integrated with the ALU. We avoid these problems by exploiting the properties of half-adder form. Sums in half-adder form can be computed very quickly (with the delay of a half adder), yet they have enough structure so that many of the properties of the final sum can be easily detected. Our zero detector is faster than any previously described, requires only a small amount of additional circuitry in the ALU, and adds little or nothing to the overall delay of the ALU. We also examine some of the architectural implications of early zero detection: faster branching, more instruction-level parallelism, more powerful instructions, and reduced hardware needs for supporting speculative execution.