Integrating a misprediction recovery cache (MRC) into a superscalar pipeline
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
ACM Transactions on Embedded Computing Systems (TECS)
The performance of pollution control victim cache for embedded systems
Proceedings of the 21st annual symposium on Integrated circuits and system design
Optimal bypass monitor for high performance last-level caches
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. Today on-chip caches typically consume from 20% to 50% of the total chip area and their cost is mostly a function of the chip area they consume. Clearly, any technique which can maintain memory performance and reduce chip area requirements is extremely important. In this paper we present two novel cache architectures called pollution control caching (PCC) and pollution control caching plus victim buffering (PCC+VB). We have used trace driven simulation to obtain miss ratio statistics and we developed analytical models of the expected clock cycles per instruction (E[CPI]) for each architecture and cache size studied. Analytical models were parameterized with the results of our trace driven simulation. These models incorporate provisions to study the effect that on-chip cache size has on access time, and the effect that this and different main memory latencies have on the E[CPI]. Chip area models were also developed for each architecture and used as a basis for comparison. Finally, we used ANOVA techniques to better quantify the differences in the miss rate performance of the cache sizes and cache architectures studied. Our research has shown that, given the constraints of our design space, PCC+VB equipped caches can match the miss rate performance and E[CPI] of direct napped caches that require greater than five times the silicon area.