Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Genetic programming: an introduction: on the automatic evolution of computer programs and its applications
Distributed Genetic Algorithms
Proceedings of the 3rd International Conference on Genetic Algorithms
Empirical Studies of Neighborhood Shapes in the Massively Parallel Diffusion Model
SBIA '02 Proceedings of the 16th Brazilian Symposium on Artificial Intelligence: Advances in Artificial Intelligence
A massively parallel architecture for distributed genetic algorithms
Parallel Computing - Special issue: Parallel and nature-inspired computational paradigms and applications
Novel hardware-based approaches for intrusion detection
ICCOM'05 Proceedings of the 9th WSEAS International Conference on Communications
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
Reconfigurable communication networks in a parametric SIMD parallel system on chip
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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Over the last decades Genetic Algorithms (GA) and Genetic Programming (GP) have proven to be efficient tools for a wide range of applications. However, in order to solve human-competitive problems they require large amounts of computational power, particularly during fitness calculations.In this paper I propose the implementation of a massively parallel model in hardware in order to speed up GP. This fine-grained diffusion architecture has the advantage over the popular Island model of being VLSI-friendly and is therefore small and portable, without sacrificing scalability and effectiveness. The diffusion architecture consists of a large amount of independent processing nodes, connected through all X-net topology, that evolve a large number of small, overlapping sub-populations. Every node has its own embedded CPU, which executes a linear machine code representation of the individuals. Preliminary simulation results (low-level VHDL simulation) indicate a performance of 10.000 generations per second (depending on the application). One node requires 10-20.000 gates including tile CPU (also application dependent), which makes it possible to fit up to 2.000 individuals in one FPGA (Virtex XC2V10000).