Numerical recipes: the art of scientific computing
Numerical recipes: the art of scientific computing
Digital signal processing applications with the TMS320 family; Vol. 1
Digital signal processing applications with the TMS320 family; Vol. 1
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
DFT/FFT and Convolution Algorithms: Theory and Implementation
DFT/FFT and Convolution Algorithms: Theory and Implementation
The Microarchitecture of Pipelined and Superscalar Computers
The Microarchitecture of Pipelined and Superscalar Computers
The Fastest Fourier Transform in the West
The Fastest Fourier Transform in the West
Improved twiddle access for fast fourier transforms
IEEE Transactions on Signal Processing
WSEAS Transactions on Circuits and Systems
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In microprocessor-based systems, memory access is expensive due to longer latency and higher power consumption. In this paper, we present a novel FFT algorithm to reduce the frequency of memory access as well as multiplication operations. For an N-point FFT, we design the FFT with two distinct sections: (1) The first section of the FFT structure computes the butterflies involving twiddle factors WJN (j 驴 0) through a computation/partitioning scheme similar to the Hoffman coding. In this section, all the butterflies sharing the same twiddle factor will be clustered and computed together. In this way, redundant memory access to load twiddle factors is avoided. (2) In the second section, the remaing (N - 1) butterflies involving the twiddle factor WON are computed with a register-based breadth-first tree traversal algorithm. This novel twiddle-factor-based FFT is tested on the TI TMS320C62x digital signal processor. The results show that, for a 32-point FFT, the new algorithm leads to as much as 20% reduction in clock cycles and an average of 30% reduction in memory access than that of the conventional DIF FFT.