DFT/FFT and Convolution Algorithms: Theory and Implementation
DFT/FFT and Convolution Algorithms: Theory and Implementation
Twiddle-Factor-Based FFT Algorithm with Reduced Memory Access
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Novel CORDIC-Based Systolic Arrays for the DFT and the DHT
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Computer
Reconfigurable VLSI architecture for FFT processor
WSEAS Transactions on Circuits and Systems
A novel linear array for discrete cosine transform
WSEAS Transactions on Circuits and Systems
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Discrete Fourier Transformations with Weight
ICIC '11 Proceedings of the 2011 Fourth International Conference on Information and Computing
A novel method for calculating the convolution sum of two finitelength sequences
IEEE Transactions on Education
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The improvement in speed and power for calculating discrete Fourier transformation using circular convolution is well established, but all the work so far been reported are at FPGA (gate) level. In this paper ASIC implementation of high speed processor for calculating Discrete Fourier Transformation (DFT) based on circular convolution architectures is reported for the first time. The IEEE-754 single precision format was considered for the representation of the twiddle factors. The improvement of the speed for floating point multiplication/addition was achieved by canonical sign digit implementation methodology, which reduced the stages of operation significantly. The functionality of these circuits was checked and performance parameters such as propagation delay, dynamic switching power consumptions were calculated by spice spectre using standard 90nm CMOS technology. The implementation methodology ensure substantial reduction of propagation delay in comparison with systolic array and memory based implementation, most commonly used architectures, reported so far, for DFT processors. The propagation delay of the resulting 16 point DFT processor is only 23.79µs while the power consumption of the same was 14.32mW only for a layout area of ∼12mm2. Almost 50% improvement in speed from earlier reported DFT processors, e.g. systolic array and memory based implementation methodology, has been achieved.